1. Field of the Invention
The present invention relates to a computer architecture which contains a coherency control module that allows a writeback cache to be implemented into existing architectures and which maintains coherency between the writeback cache and the main memory.
2. Description of the Related Art
Microprocessor performance can be greatly enhanced by use of an on-chip cache memory. The cache provides a local high speed memory store for storage of data and instructions used by a central processing unit (CPU) or microprocessor during normal execution of a sequence of instructions. In a conventional computer system, a main memory is also coupled to the CPU via a bus for main storage of program instructions and data. Access to the main memory by the CPU is typically much slower than access to the cache.
An important function of a cache subsystem is the maintenance of cache coherency. The contents of cache memory must be consistent with the corresponding locations in main memory. Cache coherency may be affected if devices other than the CPU attempt to write into main memory. Many methods exist for maintaining cache coherency in conventional computer systems. Once such method is embodied in the cache subsystem of the i486 brand microprocessor manufactured by Intel Corporation. i486 is a registered trademark of Intel Corporation. When writing data, the i486 writes data to both the cache and the main memory to maintain coherency between the two memory devices. Such a system is typically referred to as writethrough cache.
The bus in a typical computer system architecture is used to couple the CPU and other devices such as a direct memory access (DMA) controller and other bus master cards to main memory through a memory controller. In systems that include cache, signals are typically provided on the bus for supporting the cache subsystem and specifically for supporting the cache coherency logic. These signals are used by the CPU and the memory controller to determine for a CPU memory access request whether the requested data may be found in the cache or whether an access to main memory must be initiated. An access to main memory must be initiated if the requested location in main memory is updated by a device other than the CPU, because the corresponding location in the cache memory is no longer valid. The bus used in systems supporting an i486 microprocessor provide these cache control signals on the bus. It will be apparent to those skilled in the art that systems supporting a different brand of microprocessor also provide cache control signals on the bus.
Although buses, processors and memory controllers fully supporting cache subsystems are well-known in the art, other computer systems not supporting cache memory are also well known. One well-known microprocessor used in conventional non-cache supporting computer systems is the 386 brand microprocessor manufactured by Intel Corporation. 386 is a registered trademark of Intel Corporation. It will be apparent to those of ordinary skill in the art that other processors not supporting a cache subsystem exist in the prior art. Because these processors do not support a cache subsystem, the bus coupling these processors and other devices to main memory through a memory controller do not support cache control signals. In non-cache supporting systems, each memory access request made by the CPU or other memory access devices cause the memory controller to initiate an access to main memory. These systems therefore typically operate much more slowly than cache supporting computer systems. Thus, conventional computer systems either fully support a cache subsystem wherein both the processor and the bus support caching, or other conventional systems do not support caching wherein neither the processor nor the bus support caching.
In some situations, it is advantageous to implement a hybrid computer system wherein a processor with an integrated cache is used with a non-cache supporting bus. A non-cache supporting bus is one in which the signals required to support a cache are missing. Such a hybrid system could be built, for example, if a 386 brand microprocessor is upgraded to an i486 brand microprocessor thereby gaining the benefit of a faster processor and one capable of executing i486 compatible software. It will be apparent to those skilled in the art that other situations may arise whereby a processor with an integrated cache may advantageously be used with a non-cache supporting bus. In spite of the advantages of a hybrid system configuration, conventional techniques can not support this hybrid configuration. In order to use the cache subsystem on a processor with an integrated cache, cache control signals must be present on the bus to maintain cache coherency. This is because a memory access device, such as a DMA controller or other processor may initiate a memory access that modifies main memory and thereby renders the data in cache obsolete.
It is also desirable to improve the performance of existing computer system that support a writethrough cache subsystem. Although a writethrough cache improves the efficiency of the processor, the system is still slowed down by the extra cycles required to store the data in both the cache and the main memory. There exist another type of cache subsystem commonly referred to as a writeback cache which improves the speed of the processor. During the write routine of a writeback cache subsystem, the data is stored in the cache if the address of the data corresponds to an address in the cache memory. The cache marks the modified data which is typically referred to as a "dirty" cache line. The cache does not store the dirty data in the main memory until the processor writes new data in the same address, or the processor flushes the whole cache. A lack of coherency will occur if an external device reads the contents of the main memory before the cache writesback the dirty data. 386 and i486 based systems are presently not equipped to fully support a processor with writeback cache.
It would be desirable to upgrade existing 386 or i486 based computer systems to incorporate a processor with writeback cache and to maintain coherency between the writeback cache and the main memory.